Overview: Responsibilities:

• Responsible for Co Wo S_S, Co Wo S_L (EFB), FOPLP, In FO/WLFO, FCBGA, LGA and Chiplet package feasibility, development, manufacturing readiness for New Product bring up at manufacturing site and qualification to production together with Packaging team. Manage NPI to LVM to HVM, Supplier Qualification, with First pass and Issue free production for 6 months to ensure Repeatability and Reproducibility.
• Responsible for HVM packaging Yield, Quality to Meet and Exceed Target for all metrics, cost and operation productivity improvements and sustaining activities.
• Drive packaging process baseline standardization and Issue prevention/resolution through continuous improvement to achieve “best in class” quality/yield performance across OSAT’s.
• Responsible for the packaging interaction activities among assembly, bump, 3D IC, HBM and wafer fab, wafer sort, functional test and Mark/Pack.
• Drive Assembly manufacturer to enhance process, equipment & material capability for future generation/technology products and capabilities ahead of roadmap needs.
• Best known methods/lesson learnt fan out between sites for standardization & drive for Non-issue based CIP’s.
• Responsible for strategic supplier management. Quarterly Scorecard/ Performance management reviews for Packaging/Bumping and Material Suppliers.
• Spec management, including review/update under Back End Engineering responsibilities.
• Responsibilities will include defining and managing Key Program deliverables/schedules/budget/Analyze program risk and opportunities & monitor progress to drive to ensure goals are met.
• System Integration with Data Analytics to have real time update and control over supplier overall performance.
• Self-Driven/Lead, manage, develop a motivated high performance team with Improved bench strength and drive to achieve Next 5% to continue to stay ahead of the curve. Reach-out before Reached with respect to Rn R.
• Build effective team and strategic relationship across the network. Manage and resolve conflicts.
• The applicant must be a team player with a commitment to meeting deadlines and an aptitude to thrive in a fast-paced multi-tasking environment.
• Job may include other duties as assigned/ deemed fit by supervisor.

• Minimum 20 years+ experience in Packaging/Bumping/Materials management.
• Experience in In FO or 2.5D/3D Bump/TSV/Packaging or WLFO, Flip Chip BGA/LGA process knowledge and Chip-Packaging Interaction knowledge with min total 12 years Packaging/Assembly NPI to HVM work experience.

• Experience in Co-working/managing horizontally across multiple internal functional organization.
• Team player with a commitment to meeting deadlines/Lead & Drive for solutions and an aptitude to thrive in a fast-paced multi-tasking environment.
• Creative, Self-Driven, highly motivated individual with demonstrated ability to independently manage complex engineering tasks.
• Strong interpersonal communication, analytical, project management, task & time management and excellent executive presentation & communication skills.

• Familiar with DOE and JMP & technical report writing
• Ability and Willingness to travel internationally is required

• Bachelor/MS degree in Mechanical Electrical or Material or Chemical Engineering

Qualifications: